Fares Elsabbagh

Jaewoong Sim

**NOTE1: If you are attending MICRO tutorial, please join <vortex-dev@lists.gatech.edu> or send an email to <vortexgpu@cc.gatech.edu>. Further instructions will be distributed by this mailing list.** 

 **NOTE2: Please see [tutorial github](https://github.com/vortexgpgpu/vortex_tutorials) for the updated tutorial information.** 

 **Data: 2021-10-18** (10:00 AM EDT- 1:00 PM EDT) 

 **Organizers:**

 Hyesoon Kim (Georgia Institute of Technology) 

Blaise Tine (Georgia Institute of Technology) 

Jeff Young (Georgia Institute of Technology) 

Ruobing Han (Georgia Institute of Technology)_

Liam Cooper (Georgia Institute of Technology) 

 **How to register: ** [MICRO54 register link](https://www.microarch.org/micro54/attend/register.php)  

 **Description:**

 Vortex is an open source Hardware and Software project to support GPGPU based on RISC-V ISA extensions. Currently Vortex supports OpenCL/CUDA and it runs on FPGA. The vortex platform is highly customizable and scalable with a complete open source compiler, driver and runtime software stack to enable research in GPU architectures. 

 

Vortex Homepage: [http://vortex.cc.gatech.edu/](http://vortex.cc.gatech.edu/) 

Vortex Github: [https://github.com/vortexgpgpu/](https://github.com/vortexgpgpu/) 

 

**Tentative Tutorial schedule:**  

 

Part-1  (2 hours)   

20 min: Introduction of vortex and GPGPU backgrounds (Hyesoon Kim)  

20 min: Vortex microarchitecture Basic (Blaise Tine)  

30 min: Vortex code structure review  (Blaise Tine)  

20 min: Introduction of Vortex software stack (Blaise Tine, Ruobing Han)  

20 min: SimX + running OpenCL/CUDA on vortex (Hyesoon Kim, Ruobing Han)  

10 min: break  

Part-II: Hands on exercise  

30 min : Hands on session: running vortex on FPGA  (Blaise Tine + Jeff Young)  

(tutorial assignments #1-2)  

30 min: Hands on exercise: Tutorial assignment #3    (Liam Cooper + Ruobing Han + Santosh Srivatsan) 

 **Request for Accounts** 

 For the tutorial registered users, we will provide temp accounts. The information will be sent out later. 

Authors: Rohit Mundada, Hitharth Shajwani, Samarth Agarwal (BITS Pilani)

64-bit Extension for Vortex

Simx Implementation of Cache in Vortex and a HW Prefetcher Design

Learn more about our project, see our source code, get your questions answered, and interact with our community!

You can view VORTEX's source code on our GitHub page.

GitHub

The mailing list provides a direct way to communicate with the developers, users, and contributors. Get your questions answered here.

Mailing List

Hyesoon Kim

Blaise Tine

Jeffrey Young

Details can be found [here](https://vortex.cc.gatech.edu/micro2024/).

Vortex Workshop and Tutorial at MICRO 2024

Vortex 2.0 is now [public](https://github.com/vortexgpgpu/vortex)

Vortex 2.0 has been released

Details can be found [here](https://vortex.cc.gatech.edu/micro2023/)

Vortex tutorial at MICRO 2023

Vortex paper presented at ASPLOS 2023

Details can be found [here](https://github.com/vortexgpgpu/vortex_tutorials)

Vortex tutorial at MICRO 2022

See the workshop presentation [here](https://oscar-workshop.github.io/files/OpenGPUResearch_OSCAR22.pdf)

Vortex workshop at OSCAR 2022

Vortex paper has been accepted by MICRO 2021

Vortex paper at MICRO 2021

3 Vortex-related papers are shown in CARRV-2021. They can be found in the "Recent Publications" page.

3 Vortex-related papers are in CARRV-2021

A Scalable Multicore RISC-V GPGPU Accelerator for High-End FPGAs is selected to present a Designer Track poster at one of the DIET Poster Receptions at the 2021 DAC, December 5-9.

Vortex will be in DAC DIET in 2021

The Vortex Github is public now! Please check it out.

Vortex is public on Github

Vortex GitHub has migrated into a public version of GitHub. The git version of Vortex is tested on Arria 10 FPGA.

Vortex GitHub is now public.

Vortex paper is accepted as a poster at HotChips.![https://www.hotchips.org/program/](https://www.hotchips.org/program/ "https://www.hotchips.org/program/")

Vortex paper gets poster at HotChips

Vortex ArXiv paper gets media attention.

See the following articles: [https://www.hackster.io/news/vortex-brings-the-risc-v-isa-to-the-world-of-opencl-compatible-general-purpose-gpus-389f8adc0f98](https://www.hackster.io/news/vortex-brings-the-risc-v-isa-to-the-world-of-opencl-compatible-general-purpose-gpus-389f8adc0f98 "https://www.hackster.io/news/vortex-brings-the-risc-v-isa-to-the-world-of-opencl-compatible-general-purpose-gpus-389f8adc0f98")

[https://riscv.org/2020/03/vortex-brings-the-risc-v-isa-to-the-world-of-opencl-compatible-general-purpose-gpus-gareth-halfacree-hackster-io/](https://riscv.org/2020/03/vortex-brings-the-risc-v-isa-to-the-world-of-opencl-compatible-general-purpose-gpus-gareth-halfacree-hackster-io/ "https://riscv.org/2020/03/vortex-brings-the-risc-v-isa-to-the-world-of-opencl-compatible-general-purpose-gpus-gareth-halfacree-hackster-io/")

[https://www.khronos.org/news/permalink/cornells-vortex-opencl-compatible-risc-v-gpgpu](https://www.khronos.org/news/permalink/cornells-vortex-opencl-compatible-risc-v-gpgpu "https://www.khronos.org/news/permalink/cornells-vortex-opencl-compatible-risc-v-gpgpu")

Vortex ArXiv paper gets media attention

Aditya Potluri

Varsha Singhania

Udit Subramanya

Nayan Sivakumar Nair

Hanran Wu

Hena Naaz

Euijun Chung

Austin T Weatherly 

Pranav V C

Praeek Udpadhay

Rijul Radhu

Shreyas Hebbar S

Amod Nijasure

Haotian Sheng

Fadi Alzammar

Rushabh Jignesh Shah

Gaurav Basu

Yahya S Al Hinai

Naga Ram Jaswanth Chunduru

Shashank K Holla

Atrey Hosmane

Varun Saxena

Sibi Renganatth Sudhakar

Lohith Artham

Swetha Rajagopalan

Austin T Weatherly

Vandita A Shetty

Marcus Zhou

John Z Lu

Hitarth Girish Shajwani

Arvind Nataraj Sivasankar

Rohit Rahul Mundada

Santosh Raghav Srivatsan

Jun Chen

Bhanu Garg

Swetha Rajagoplan

Saurabh Singh

Venkata Hanuma Balemarthy

Mihir Vora Ketan

Tallapragada Srikar S

Lingala Navneet

Eshed Roye D

Rahul Hardikar

Pragnya Akkulu

Liam Cooper

Hanning Chen

Krishna Yalamarthy

Roye Eshed

Xingyang Liu

Malik Burton

Taejoon Park

Ayden Marshall

Gyubin Jason Choi

Carter Montgomery

J.T. Parrish

Apurve Chawda

Will Gulian

Yaotian Feng

Saloni Oswal

Santhosh Kumar

Yaotian Feng 

Kanghong Yan

Priyadarshini Roshan

Ethan Lyons

Euna Kim

Da Eun Shim

Lingjun Zhu

Sung Kyu Lim

Bahar Asgari

Sudhakar Yalamanchili

LLNL

Samsung

Intel

SiliconArts

Oak Ridge National Laboratory

Vortex is an open-source hardware and software project to support GPGPU based on RISC-V ISA extensions. Currently Vortex supports OpenCL and it runs on FPGA. The vortex platform is highly customizable and scalable with a complete open-source compiler, driver and runtime software stack to enable research in GPU architectures.

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Chihyo (Mark) Ahn

Shinnung Jeong

Ruobing Han

Jaewon Lee

Eric Lorimer

Nicholas Parnenzini

Vortex: OpenCL Compatible RISC-V GPGPU

**Date:** 2022-10-1

**Organizers:**

Hyesoon Kim (Georgia Institute of Technology)

Blaise Tine (Georgia Institute of Technology)

Jeff Young (Georgia Institute of Technology)

Ruobing Han (Georgia Institute of Technology)

Liam Cooper (Georgia Institute of Technology)

Sam Jijina (Georgia Institute of Technology)

**Description:**

Vortex is an open-source hardware and software project to support GPGPU based on RISC-V ISA extensions. Currently, Vortex supports OpenCL/CUDA and it runs on FPGA. The Vortex platform is highly customizable and scalable with a complete open-source compiler, driver and runtime software stack to enable research in GPU architectures. As an application session, we will also have how to run drone applications on FPGA.

**Vortex Homepage:** [http://vortex.cc.gatech.edu/](http://vortex.cc.gatech.edu/ "http://vortex.cc.gatech.edu/")

**Vortex Github:** [https://github.com/vortexgpgpu/](https://github.com/vortexgpgpu/ "https://github.com/vortexgpgpu/")

**Tutorial schedule:**

_**8:00**_-8:30 Intro and GPU background

8:30-9:00 Vortex Microarchitecture

9:00-10:00 Vortex Code Review

10:00-10:20 Q&A and Break

10:20-10:30 Vortex Software stack

10:30-11:00 CupBop/ Running OpenCL/CUDA on Vortex

11:00-11:10 Vortex FPGA demo

1:10-11:30 Tutorial assignments and discussions for academic usages with Vortex

11:30-12:00 Drone applications

**Tutorial Repository:**

[https://github.com/vortexgpgpu/vortex_tutorials](https://github.com/vortexgpgpu/vortex_tutorials "https://github.com/vortexgpgpu/vortex_tutorials")

Tutorial for Open-source RISC-V-based GPGPU: Vortex and Drone Applications on FPGA

**Organizers:**

Hyesoon Kim (Georgia Institute of Technology)

Blaise Tine (University of California, Los Angeles)

Jeff Young (Georgia Institute of Technology)

Liam Cooper (Georgia Institute of Technology)

Chihyo (Mark) Ahn (Georgia Institute of Technology)

Shinnung Jeong (Georgia Institute of Technology)

**Tutorial schedule:**

1:00-1:30 Intro and GPU Background

1:30-2:00 Vortex Microarchitecture

2:00-3:00 Vortex Code Review

3:00-3:20 Q&A and Break

3:20-3:30 Vortex Software Stack

3:30-4:00 CupBop/Running OpenCL/CUDA on Vortex

4:00-4:10 Vortex FPGA demo

4:10-4:30 Tutorial Assignments and Discussions for Academic Usages with Vortex

4:30-5:00 Hands-on Exercises

***

**More details can be found at the tutorial repository:** [https://github.com/vortexgpgpu/vortex_tutorials](https://github.com/vortexgpgpu/vortex_tutorials "https://github.com/vortexgpgpu/vortex_tutorials")

Open-Source RISC-V Based GPGPU (Vortex) and Their Usage Cases

### Organizers:

** Hyesoon Kim (Georgia Institute of Technology) **

** Blaise Tine (University of California, Los Angeles) **

** Jeff Young (Georgia Institute of Technology) **

** Jaewon Lee (Georgia Institute of Technology) **

** Seonjin Na (Georgia Institute of Technology) **

** Liam Cooper (Georgia Institute of Technology) **

** Chihyo (Mark) Ahn (Georgia Institute of Technology) **

### Schedule:

_**08:00-08:20**_ | **Introduction and GPU Background**

_**08:20-09:20**_ | **Vortex Microarchitecture and Software Stack**

_**09:20-09:40**_ | **CuPBoP: Running OpenCL/CUDA on Vortex**

_**09:40-10:00**_ | **Q&A Session**

_**10:00-10:20**_ | **Coffee Break**

_**10:20-11:00**_ | **Tutorial Assignments / Hands-on Exercises**

_**11:00-12:00**_ | **Vortex Workshop Presentations _(3 Speakers)_**

**More details for Tuotrial will be updated at the tutorial repository:** [Vortex Tutorial Github](https://github.com/vortexgpgpu/vortex_tutorials "https://github.com/vortexgpgpu/vortex_tutorials")

----

### Workshop Presentation Schedule

Each presentation will consist of  a 15-minutes talk followed by a 5-minutes Q&A session.



| Time | Speaker | Institution | Title |
| --- | --- | --- | --- |
| 11:00\~11:20 | **Davy Million** | Université Grenoble Alpes | Preliminary Integration of Vortex within the OpenPiton Platform |
| 11:20\~11:40 | **Matt Sinclair** | University of Wisconsin-madison | Prototyping Mechanisms to Co-design Power Management and Performance in Accelerator-Rich Systems |
| 11:40\~12:00 | **Martin Troiber** | Technical University of Munich | Analysis of the RISC-V Vector Extension for Vulkan Graphics Kernels on the Vortex GPU |


#### 1. Preliminary Integration of Vortex within the OpenPiton Platform
**Authors:** \*[Davy Million](mailto:davy.million@cea.fr), \*[César Fuguet](mailto:cesar.fuguettortolero@cea.fr), \*[Adrian Evans](mailto:adrian.evans@cea.fr), ‡[Jonathan Balkind](mailto:jbalkind@ucsb.edu), ‡[Frédéric Petrot](mailto:frederic.petrot@univ-grenoble-alpes.fr)

**Institution:** \*Univ. Grenoble Alpes, CEA, List, †University of California, Santa Barbara , ‡Univ. Grenoble Alpes, TIMA

**Abstract** 

This paper details the initial integration of the Vortex GPU core into the OpenPiton many-core research platform. Vortex, an open-source RISC-V-based GPU, was connected to OpenPiton using an AXI-4 to P-Mesh bridge, enabling shared memory access between Vortex and general-purpose processors without data copying. The integration allows for heterogeneous computing but faces performance bottlenecks due to the non-pipelined bridge, particularly for workloads exceeding the L1 cache size. Initial benchmarks using a vector addition kernel showed that while Vortex can handle memory latency in standalone mode, performance drops when integrated with OpenPiton due to cache miss serialization. Future improvements include pipelining the bridge and enhancing memory coherence mechanisms to optimize performance in this open-source heterogeneous CPU/GPU system. </details>

#### 2. Prototyping Mechanisms to Co-design Power Management and Performance in Accelerator-Rich Systems

**Authors:** [Matt Sinclair](mailto:sinclair@cs.wisc.edu),  [Shivaram Venkataraman](mailto:shivaram@cs.wisc.edu)

**Institution:** University of Wisconsin–Madison


**Abstract**

In recent years, to reach performance goals modern computing systems are increasingly turning to using large numbers of compute accelerators, which offer greater power efficiency and thus enable higher performance within a constrained power budget. However, using accelerators increases heterogeneity at multiple levels, including the architecture, resource allocation, competing user needs, and manufacturing variability. Accordingly, current and future systems need to efficiently handle many simultaneous jobs while balancing PM and multiple levels of heterogeneity. In recent work, we have demonstrated the extent of this variability in modern accelerator-rich systems (SC'22) and shown how to embrace variability in cluster-level job schedulers (SC'24). This work significantly improves the efficiency of modern systems for a range of ML workloads.
However, scheduling jobs more efficiently at the software and runtime layers is limited in its ability to quickly, dynamically change policies as cluster conditions evolve. A major limiter to further improving efficiency is the lack of standards for exposing power information in modern accelerators. Thus, for future systems we propose to build on the insights generated by our optimizations for current systems, and apply co-design that makes the hardware, software, and runtime layers aware of the variance in the systems. To do this, we will design a standard for accelerators to expose PM information from the hardware to the software and runtime. Using this information, instead of performing PM locally, we plan to develop a global power management scheme to enable optimal PM decisions across accelerators and further reduce performance variability. In this talk, I will discuss our ongoing efforts at harnessing variability in accelerator-rich systems and how we hope to leverage the Vortex open-source GPU hardware to prototype our proposed ideas. </details>

#### 3. Analysis of the RISC-V Vector Extension for Vulkan Graphics Kernels on the Vortex GPU
**Authors:** \*[Martin Troiber](mailto:m.troiber@tum.de), †[Hyesoon Kim](mailto:hyesoon@cc.gatech.edu), ‡[Blaise Tine](mailto:blaisetine@cs.ucla.edu), \*[Martin Schulz](mailto:schulzm@in.tum.de)

**Institution:** \*Technical University of Munich, †Georgia Institute of Technology , ‡University of California, Los Angeles

**Abstract**

In this work we analyze the benefits of the RISC-V vector extension for accelerating 3D graphics kernels. Our work uses open-source projects for the graphics driver (SwiftShader), GPU (Vortex) and instruction set architecture (RISC-V). For our purpose we modified the graphics driver to generate kernels with vector instructions. We then extended the GPU simulator to execute the vectorized kernels. To augment our simulated performance measurements we used a CPU (Kendryte K230) with the same vector instructions. On both platforms we analyzed the popular gears example from the Vulkan demo scenes. In GPU simulation, we could reduce the cycle count by up to 54% compared to scalar kernels. On the CPU we increased the frame rate of the gears demo scene by over 85% compared to scalar execution. The measured 13fps@1080p is the highest frame rate achieved using SwiftShader on any RISC-V single board computer.</details>

----
### Call for Papers for Vortex Workshop

The Vortex Workshop aims to bring together Vortex developers, contributors, and users from academia and industry to discuss Vortex-related research. The Vortex Tutorial will be held in conjunction with the workshop, providing an introduction to Vortex and its use in research and teaching. The workshop will offer an opportunity to share ongoing efforts in Vortex development or research using Vortex, thereby fostering the Vortex or open-source GPGPU community.

#### Topics of interest for the Vortex Workshop include, but are not limited to:

* Design and implementation of Vortex GPGPU
* OpenCL/CUDA running on Vortex
* Compiler optimizations for Vortex
* Memory hierarchy and management in Vortex GPGPU
* Benchmarking and performance evaluation
* Applications and case studies using Vortex
* Security and reliability in GPGPU architecture
* Comparison of Vortex with other GPGPU architectures
* FPGA/ASIC implementation of Vortex

#### Submission Guidelines:

Authors are invited to submit 2-page papers, which must be formatted in accordance with the ACM two-column style.
ACM Word or LaTeX style templates are available [here](https://www.acm.org/publications/proceedings-template).

**Note:** Workshop publications do not preclude publishing at future conference venues.

#### Important Dates:

* Paper submission deadline: September 5th, 2024, 23:59 EDT
* Author notification: September 17th, 2024
* Workshop date: November 3rd, 2024, 8:00 AM CST – 12:00 PM CST

#### Submission Link:

* [Easychair](https://easychair.org/my/conference?conf=vortex20240 "https://easychair.org/my/conference?conf=vortex20240")

#### Organizing Committee:

* General Chair: Hyesoon Kim (Georgia Tech), Blaise Tine (UCLA)
* Session Chair: Jaewon Lee (Georgia Tech)
* Web Chair: Seonjin Na (Georgia Tech)

#### Contact Information:

For more information about the submission on Vortex Workshop, please send email to [vortex_submission@groups.gatech.edu](mailto:vortex_submission@groups.gatech.edu)

Vortex Tutorial at MICRO 2023

Open-Source RISC-V Based GPGPU: Vortex and Drone Applications on FPGA

Vortex Tutorial at MICRO 2022

Vortex Tutorial at MICRO 2021

Blogs

64-bit Extension for Vortex

Simx Implementation of Cache in Vortex and a HW Prefetcher Design